1. Field of the Invention
The present invention relates to a semiconductor device, and, more particularly, to an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) using an SOI (Silicon On Insulator) substrate.
2. Description of the Related Art
An MOSFET formed on a conventional SOI substrate is formed in a process similar to the fabrication process for an MOSFET on an ordinary bulk substrate (Si substrate). For example, there has been proposed a method of forming an MOSFET on an SOI substrate using a process similar to the process for the ordinary bulk substrate (see L. T. Su et al., Proc. IEDM 93, pp. 723-726 (1995)). The outline of the method will be given below referring to FIG. 9.
An SOI substrate 200 having a BOX (Buried Oxide) layer 204 and an SOI layer 206 deposited on an Si substrate 202 in order is prepared (FIG. 9A). The BOX layer 204 is a buried silicon oxide film and the SOI layer 206 is a silicon layer formed on the BOX layer.
The SOI layer 206 of the SOI substrate 200 is subjected to sacrificed oxidation and the sacrificed-oxidation portion is removed to adjust the thickness of the SOI layer (not shown). An oxide film to be a device isolation region 208 is formed by LOCOS (Local oxidation) or STI (Shallow Trench Isolation). The regions that are surrounded by this device isolation region become an NMOS forming region 210 and a PMOS forming region 212 (FIG. 9B).
Next, threshold-controlled ion injection is performed on each of the NMOS forming region 210 and the PMOS forming region 212 to form a P well region 214 and an N well region 216. Then, a gate oxide film 218 is formed. The gate oxide film 218 may be formed before the threshold-controlled ion injection. A non-doped polysilicon film is formed on the gate oxide film 218 and is etched using a resist pattern of a desired gate pattern, thereby forming a non-doped silicon film 220 (FIG. 9C).
Source-drain ion injection is performed on each of the NMOS forming region 210 and the PMOS forming region 212. As the illustrated example has an LDD (Lightly Doped Drain) structure, an impurity of a low concentration is doped into the NMOS forming region 210 and the PMOS forming region 212 first with a patterned polysilicon film as a mask, thereby forming an n− region 222 and a p− region 224. Then, sidewalls 226 are formed on the sides of the polysilicon film 220 by an insulating film, and with the sidewalls 226 and the polysilicon film 220 as masks, ion injection is performed on the NMOS forming region 210 and the PMOS forming region 212 to form an n+ region 228 and a p+ region 232 which become source and drain regions. At this time, an impurity is doped into the non-doped silicon film 220 by ion injection, so that an n+ polysilicon film 230 which becomes a gate electrode doped with an n type impurity is formed on the NMOS side and a p+ polysilicon film 234 which becomes a gate electrode doped with a p type impurity is formed on the PMOS side (FIG. 9D).
Next, a silicide film 236 is formed to reduce the sheet resistances of the source and drain regions and the gate electrode (FIG. 9E).
After an interlayer insulating film 238 is deposited, contact holes are formed and barrier metals 240 and contacts 242 are formed in the contact holes. Then, metal wires 244 are formed, thereby yielding an MOSFET (FIG. 9F).
In the SOI transistors fabricated in the above-described process, as the device size becomes smaller, a so-called short channel effect (SCE) in which the threshold voltage (Vth) falls as the gate length becomes shorter occurs. As the SCE makes a variation in threshold voltage worse, it is important to suppress the SCE.
It is known that making the SOI layer thinner is effective in suppressing the SCE (see N. Kistler et al., Solid State Electronics, vol. 39, No. 4, pp. 445-454 (1996)).
FIG. 10 is a diagram showing the relationship between the threshold voltage (Vth) roll-off (vertical axis: unit (mV)) and the gate length (horizontal axis: unit (μm)) in a semiconductor device acquired by the conventional fabrication process. The diagram shows how the Vth roll-off varies according to the value of the gate length in case where the thickness of the SOI layer is 46 nm, 95 nm and 142 nm. In this example, the Vth roll-off is the difference between the threshold voltage in case of the gate length of 10 μm and the threshold voltage at each gate length. As the SOI layer becomes thinner, the value of the Vth roll-off when the gate length becomes short gets smaller. This makes it apparent that forming the SOI layer thinner is effective to suppress the SCE.
There are several semiconductor devices known which have an insulating layer provided under the channel region. For instance, it is proposed to form an insulating layer in contact with the source or drain region and in a region deeper than the channel region in order to prevent a punch-through current from being generated by shortening the channel length (see Japanese Patent Laid-Open No. 313865/1988).
It is also proposed to form an insulating layer or a semi-insulating layer in the Si substrate under the channel region in order to improve both the punch-through characteristic and sub threshold characteristic (Japanese Patent Laid-Open No. 211902/1995).
It is further proposed to form an insulating layer in the Si substrate between the source region and the drain region in order to suppress the occurrence of the punch-through phenomenon (Japanese Patent Laid-Open No. 51198/1996).
There has been proposed a method of forming a fully-depleted type transistor which suppresses an increase in the resistances of the source and drain regions and the extension layer by making the SOI layer thinner by forming a buried oxide film (BOX oxide film) on the SOI substrate in such a way that only that portion of the film which lies under the gate electrode is located at a shallow position (Japanese Patent Laid-Open No. 2001-135821).
In case of devices whose standby power consumption is desired to be lower, such as a semiconductor device for use in a portable terminal, making the off-leak current Ioff has a higher priority over increasing the operational speed. In such a transistor with a low off-leak current set (Ioff<1E−11A/μm and threshold voltage of 0.4 V or so), making the SOI layer thinner to suppress the SCE brings about the following problems.
The following discusses a case of a fully-depleted type thin film SOI transistor. The “fully-depleted type” indicates that the SOI layer between the source and drain regions is fully depleted and generally the thickness of the SOI layer becomes about 50 nm or smaller.
The threshold voltage Vth (V) can be expressed by the following equation 1 using a potential φF (V), an elementary electric charge q (C), a flatband voltage Vfb (V), a body concentration Na (cm−3) of the SOI layer, a thickness Tsoi (nm) of the SOI layer and an oxide film capacitance Cox (F).Vth=Vfb+φF+q×Na×Tsoi/Cox  (1) 
The potential φF is the value that is acquired from φF=(EF−Ei)/q where EF (eV) is the Fermi level and Ei (eV) is the Fermi level of an intrinsic semiconductor. The value of 2×φF is called a strong inversion potential and inversion occurs when the surface potential exceeds the value of 2×φF. Vfb is the value that is acquired from Vfb=(Wm−Ws)−Qox/Cox where Wm is the gate electrode work function, Ws is the silicon work function and Qox is the interface charge density. The value of (Wm−Ws) is called a work function difference.
In case of an NMOSFET formed on an SOI substrate with the conventional structure (also called an SOI-NMOSFET), for example, n+ polysilicon (Wm: 4.15 V or so, Ws: about 4.7 V and the work function difference: −0.5 V or so) is used for the gate electrode.
FIG. 11 is a diagram showing the relationship between the gate length (vertical axis: unit (cm−3)) of an SOI-NMOSFET with the conventional structure and the threshold voltage Vth (horizontal axis: unit (μm)).
A curve (I) indicated by the one-dot chain line shows the case where an impurity is not doped in the SOI layer and a curve (II) indicated by the solid line shows the case where a p-type impurity is doped by an amount of 1E18 cm−3 or so. It is apparent from the diagram that to adjust the threshold voltage to 0.4 V or so, the concentration of the p-type impurity or the body concentration Na of the SOI layer should be set to 1E18 cm−3 or higher.
FIG. 12 is a diagram showing the relationship between the lateral profile (horizontal axis: unit of an SOI-NMOSFET with the body concentration Na of the SOI layer set to 1E18 cm−3 or higher and the impurity concentration (vertical axis: unit (cm−3)). A curve (I) indicated by the solid line shows the concentration of boron. (B) which is a p-type impurity, a curve (II) indicated by the one-dot chain line shows the concentration of arsenic (As) which is an n-type impurity and a curve (III) indicated by the broken line shows the carrier concentration. It is apparent from the diagram that the concentration of the p-type impurity in the channel region is 2E18 cm−3 or so which is considerably high.
In case where the body concentration of the SOI layer or the channel concentration exceeds 1E18 cm−3, a reduction in the mobility of carriers (the electron mobility in the NMOSFET) becomes an issue. The reduction in the mobility leads to a reduction in the drive current of transistors.
FIG. 13 is a diagram showing the relationship between the electron mobility (vertical axis: unit (cm2/(Vs))) and the vertical effective electric field (horizontal axis: unit (mV/cm)). Each of the graphs is called a mobility universal curve. The individual graphs indicated by (I) to (V) show the cases where the body concentration Na (unit: cm−3) is 3×1017 (I), 1.3×1018 (II), 1.8×1018 (III), 2.5×1018 (IV) and 3.3×1018 (V). The electron mobility becomes smaller as the body concentration gets higher. In FIG. 13, the value of the vertical effective electric field indicated by the broken-line arrow is equivalent to the case where the applied gate voltage is set to 1.0 V. It is apparent that as the body concentration Na becomes higher, the electron mobility drops considerably. Therefore, increasing the impurity concentration of the SOI layer lowers the electron mobility, resulting in a reduction in the drive current of the transistors or the transistor drive power.
As described above, the MOSFET whose off-leak current is set small and which is formed on the SOI substrate requires that the channel concentration should be increased as the transistor size becomes smaller and the film thickness becomes thinner. The increase in channel concentration however brings about a problem of lowering the transistor drive power.